1. Qt C++ for Simulation GUI
2. Write compiler and Parser for verilog and system verilog
3. Optimization for software architecture.
4. Responsible for designing, developing, and debugging on verification EDA (electronic design automation) tool for ESL/RTL SoC design.


======== Qualification ========
- Graduate school degree preferred, but not a must
- Great understanding of algorithm.

========== Key Capabilities ==========
Required:
- Proven C++ and SW engineering skills;
- Proven data structures and algorithm knowledge;

Plus:
- Proven SoC modeling and simulation knowledge;
- Analytic thinking and SW debugging skills;
- Hardware description language: SystemVerilog/Verilog