Principal Firmware Engineer – Firmware Architecture
Posted on: 4/28/2025
New Taipei
Permanent
Semiconductor
We are seeking a seasoned Principal Firmware Engineer to lead the architecture and development of firmware for next-generation Data Center and Enterprise SSD products. You will be part of an innovative team working on high-performance storage solutions, bridging advanced embedded systems knowledge with cutting-edge SSD controller technologies. This role emphasizes hands-on architecture, design validation, performance tuning, and collaboration across hardware and system teams.
Key Responsibilities:
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Define firmware architecture to support new customer-driven features and product initiatives.
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Conduct architectural studies and early-stage feasibility assessments for new functionalities.
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Work closely with hardware architects to optimize hardware/firmware interaction for IO performance, verifying results through simulation and modeling.
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Research, prototype, and implement advanced FTL algorithms and innovative SSD features.
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Tune firmware to maximize IOPS, minimize latency, and optimize power consumption under demanding enterprise workloads.
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Perform root-cause analysis of complex system-level issues using logic analyzers, protocol analyzers, and other debug tools.
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Maintain comprehensive documentation to ensure design traceability, reusability, and collaboration across teams.
What We Look For:
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Strong interpersonal skills with a focus on proactive communication and teamwork.
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Ability to manage multiple technical challenges simultaneously while driving initiatives forward.
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Clear and structured written and verbal communication, comfortable presenting complex topics.
Required Qualifications:
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Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
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Minimum 10 years of experience in embedded firmware development (C/C++/Assembly), including 5+ years in SSD or storage systems.
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Deep understanding of bare-metal and lightweight RTOS environments on multi-core SoCs.
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Expertise in NAND flash technologies (SLC, TLC, QLC), Flash Translation Layer (FTL) design, and controller firmware.
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Strong analytical and debugging capabilities in complex embedded systems.
Preferred Qualifications:
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Hands-on experience with NVMe protocol and PCIe optimization for storage.
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Knowledge of data center SSD characteristics including QoS, endurance, and latency optimization.
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Familiarity with high-level system modeling (e.g., SystemC/TLM).
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Understanding of storage security standards such as TCG Opal and hardware-based encryption (e.g., AES, PQC-ready).
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Experience with ARM Cortex-A/R/M, RISC-V, or MIPS architecture development.