Staff Engineer/Lead of DFT

What You'll Do:

• Serve as a senior member of the central DFT methodology group, responsible for developing flows across all departments and projects.
• Design methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across various IPs, chiplets, and SoC designs.
• Create automated verification test benches and sequences for DFT IP, architecting end-to-end verification solutions from static design checks to formal and sequence-based verification.
• Develop IP/block and SoC-level scan insertion flows, and script ATPG retargeting procedures, including automated quality of results (QoR) checks for implementation quality control.
• Write static timing constraints, create waivers, and devise flows for robust timing checks.
• Hire, train, and lead DFT engineers in their daily tasks to meet project goals.
• Report to the head of the Central DFT Team.
• Mentor DFT engineers throughout the project lifecycle.

What You'll Need:

• Proven technical and people management skills.
• A collaborative team player with an innovative mindset.
• Strong understanding of Verilog/VHDL and System Verilog.
• Experience with CAD and automation; proficiency in Perl for creating generic codes, along with knowledge of TCL and Python.
• Extensive experience with key DFT standards such as JTAG (1149.1/1149.6/1500), iJTAG (1687), and BIST techniques (memory BIST, logic BIST, interconnect BIST).
• Track record in integrating custom DFT logic for complex SoCs and CoWoS designs.
• Experience in SoC and IP/block level scan insertion, ATPG, and simulation of zero delay and SDF-annotated test sequences.
• Skills in scripting and reviewing SCAN/MBIST timing constraints.
• Experience developing DFT rule bases and DFT-DRC checks with SpyGlass is a plus.

Good to Have:

• Bachelor’s degree in Engineering Science, Electrical and Computer Engineering, or Computer Science.
• 12+ years of experience in complex SoC designs in RTL, DFT, or front-end capacity. Candidates with less experience may be considered for other senior technical roles.
• Extensive experience with various DFT EDA tools from Tessent, Synopsys, and Cadence.
• Knowledge of core wrapping, pattern retargeting, and packetizing ATPG techniques, as well as SSN knowledge.

Matt Hsu Manager

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	Matt.Hsu@morganphilips.com
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