Serdes Analog Design Engineer/ Technical Manager
Publiée depuis : 16/06/2025
HsinChu Taiwan
CDI
Semiconductor
1. Design and optimize transistor level circuits (analog/mixed-signal) for high-speed D2D IP.
2. Behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems.
3. Supervise layout.
4. Silicon bring up, characterization, and debugging.
5. Work with cross functional teams to bring IP from schematics to mass production ready.
6. Support customers on designing specs, benchmarking IP, integration and debugging.
※ Requirements:
1. Proficient in analog/mixed-signal circuit design principles and techniques
2. Skilled in designing high-speed analog circuits such as PLL, frequency synthesizer, TX/RX equalizer, and analog front-end.
3. Experienced in using Cadence Virtuoso tools for schematic and layout design.
4. Familiar with lab equipment and bench testing methods.
5. Knowledgeable about die-to-die communication standards such as UCIe.
6. A good team player with a strong motivation to succeed.
7. MSEE degree with 3+ years of high-speed circuit design experience.
2. Behavioral modeling (verilog/verilog-a/verilog-AMS) of circuit blocks and sub-systems.
3. Supervise layout.
4. Silicon bring up, characterization, and debugging.
5. Work with cross functional teams to bring IP from schematics to mass production ready.
6. Support customers on designing specs, benchmarking IP, integration and debugging.
※ Requirements:
1. Proficient in analog/mixed-signal circuit design principles and techniques
2. Skilled in designing high-speed analog circuits such as PLL, frequency synthesizer, TX/RX equalizer, and analog front-end.
3. Experienced in using Cadence Virtuoso tools for schematic and layout design.
4. Familiar with lab equipment and bench testing methods.
5. Knowledgeable about die-to-die communication standards such as UCIe.
6. A good team player with a strong motivation to succeed.
7. MSEE degree with 3+ years of high-speed circuit design experience.