[外商半導體設計公司] IC實體設計(APR)工程師

[外商半導體設計公司] IC實體設計(APR)工程師

工作內容:
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.

職缺需求:
1.Familiar with Synopsys (ICC2 or FC & PrimeTime)/Cadence (Innovus & Tempus)
2.Perform netlist-to-GDSII design flow, including floorplanning, power grids, clock tree synthesis, place & route, and physical verification.
3.Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, and crosstalk analysis.
4.Experience in 55/40nm design is must, and 28/16nm or below design is a plus.
5. C/C++/tcl/perl/tk/python/web design (html/css/javascript) programming skill is a plus

有興趣者歡迎與我聯繫:eva.lu@morganphilips.com，謝謝。