13 半導體 職務 台灣

1. Qt C++ for Simulation GUI 2. Write compiler and Parser for verilog and system verilog 3. Optimization for software architecture. 4. Responsible for designing, developing, and debugging on verification EDA (electronic design automation) tool for ESL/RTL SoC design. ======== Qualification ======== ...

What You'll Do: Serve as a senior member of the central DFT methodology group, responsible for developing flows across all departments and projects. Design methodologies and flows for an integrated, RTL-centric "shift left" DFT environment across various IPs, chiplets, and SoC designs. Create aut...

What You'll Do: Engage in hands-on physical design and verification tasks across various projects in advanced process nodes. Manage the setup and maintenance of project-specific ASIC development flows. Execute physical design tasks including floor-planning, place and route, clock tree synthesis (...