APR Engineer
發佈於： 2024/8/20
Taipei
Permanent
半導體
工作內容：
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
需求條件：
1.Familiar with Synopsys (ICC2 or FC & PrimeTime)/Cadence (Innovus & Tempus)
2.Perform netlist-to-GDSII design flow, including floorplanning, power grids, clock tree synthesis, place & route, and physical verification.
3.Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, and crosstalk analysis.
4.Familiar with TCL/Perl/Python scripting and design automation.
5.Experience in 55/40nm design is must, and 28/16nm or below design is a plus.
5.Candidate has 5+ years of work experience should be familiar with FinFet design, and whole chip integration is a plus
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
需求條件：
1.Familiar with Synopsys (ICC2 or FC & PrimeTime)/Cadence (Innovus & Tempus)
2.Perform netlist-to-GDSII design flow, including floorplanning, power grids, clock tree synthesis, place & route, and physical verification.
3.Experienced in hierarchical implementation, low power design flow, timing closure, IR drop analysis, and crosstalk analysis.
4.Familiar with TCL/Perl/Python scripting and design automation.
5.Experience in 55/40nm design is must, and 28/16nm or below design is a plus.
5.Candidate has 5+ years of work experience should be familiar with FinFet design, and whole chip integration is a plus