Digital Design Verification Engineer

【工作內容】
1. SoC level and IP level verification methodology
2. Develop a verification plan and Integrated verification environment
3. Integrate VIP into the SOC verification platform.

【需求條件】
1.碩士以上資訊工程、電機電子工程相關畢，5年以上相關工作經驗
2. Familiar with high speed (PCIE, USB, HDMI, DP) protocol and architecture
3. Knowledge and design experience in design verification, such as UVM/VMM/OVM and system Verilog / Verilog.
4. Scripting experience in Shell, Perl, Python
5. Knowledgeable in DDR/JPEG/H.264/H.265 is a plus.